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ffff. ATIB 1ULS1U 1 B t)Hu[]AT$
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Key is too short for device (%u < %u)
Cannot set RX flow hash configuration Hex and raw dump cannot be specified together
Cannot get module EEPROM information Cannot allocate memory for Module EEPROM data Only setting first 32 private flags
Cannot get device channel parameters no channel parameters changed, aborting
current values: tx %u rx %u other %ucombined %u
Cannot set device channel parameters Cannot allocate memory for EEPROM data Cannot allocate memory for register dump Cannot set device feature settings Cannot set device %s settings: %m
Cannot set device flag settings Could not change any device features
no ring parameters changed, aborting
Cannot set device ring parameters no coalesce parameters changed, aborting
Cannot set device coalesce parameters no pause parameters changed, aborting
Cannot set device pause parameters Cannot get current device settings Cannot get current wake-on-lan settings Cannot set new wake-on-lan settings [ speed %d ]
[ duplex half|full ]
[ port tp|aui|bnc|mii|fibre ]
[ mdix auto|on|off ]
[ autoneg on|off ]
[ advertise %x ]
[ phyad %d ]
[ xcvr internal|external ]
[ wol p|u|m|b|a|g|s|d... ]
[ sopass %x:%x:%x:%x:%x:%x ]
[ msglvl %d | msglvl type on|off ... ]
[ autoneg on|off ]
[ rx on|off ]
[ tx on|off ]
[adaptive-rx on|off]
[adaptive-tx on|off]
[rx-usecs N]
[rx-frames N]
[rx-usecs-irq N]
[rx-frames-irq N]
[tx-usecs N]
[tx-frames N]
[tx-usecs-irq N]
[tx-frames-irq N]
[stats-block-usecs N]
[pkt-rate-low N]
[rx-usecs-low N]
[rx-frames-low N]
[tx-usecs-low N]
[tx-frames-low N]
[pkt-rate-high N]
[rx-usecs-high N]
[rx-frames-high N]
[tx-usecs-high N]
[tx-frames-high N]
[sample-interval N]
[ rx N ]
[ rx-mini N ]
[ rx-jumbo N ]
[ tx N ]
-k|--show-features|--show-offload Get state of protocol offload and other features Set protocol offload and other features [ raw on|off ]
[ file FILENAME ]
[ raw on|off ]
[ offset N ]
[ length N ]
[ magic N ]
[ offset N ]
[ length N ]
[ value N ]
Show visible port identification (e.g. blinking) [ TIME-IN-SECONDS ]
[ online | offline | external_lb ]
-n|-u|--show-nfc|--show-ntuple Show Rx network flow classification options or rules [ rx-flow-hash tcp4|udp4|ah4|esp4|sctp4|tcp6|udp6|ah6|esp6|sctp6 |
rule %d ]
-N|-U|--config-nfc|--config-ntuple Configure Rx network flow classification options or rules rx-flow-hash tcp4|udp4|ah4|esp4|sctp4|tcp6|udp6|ah6|esp6|sctp6 m|v|t|s|d|f|n|r... |
flow-type ether|ip4|tcp4|udp4|sctp4|ah4|esp4
[ src %x:%x:%x:%x:%x:%x [m %x:%x:%x:%x:%x:%x] ]
[ dst %x:%x:%x:%x:%x:%x [m %x:%x:%x:%x:%x:%x] ]
[ proto %d [m %x] ]
[ src-ip %d.%d.%d.%d [m %d.%d.%d.%d] ]
[ dst-ip %d.%d.%d.%d [m %d.%d.%d.%d] ]
[ tos %d [m %x] ]
[ l4proto %d [m %x] ]
[ src-port %d [m %x] ]
[ dst-port %d [m %x] ]
[ spi %d [m %x] ]
[ vlan-etype %x [m %x] ]
[ vlan %x [m %x] ]
[ user-def %x [m %x] ]
[ action %d ]
[ loc %d]] |
delete %d
Show time stamping capabilities -x|--show-rxfh-indir|--show-rxfh Show Rx flow hash indirection and/or hash key Set Rx flow hash indirection and/or hash key [ equal N | weight W0 W1 ... ]
[ hkey %x:%x:%x:%x:%x:.... ]
Flash firmware image from the specified file to a region on the device FILENAME [ REGION-NUMBER-TO-FLASH ]
Show permanent hardware address [ rx N ]
[ tx N ]
[ other N ]
[ combined N ]
Qeuery/Decode Module EEPROM information [ raw on|off ]
[ hex on|off ]
[ offset N ]
[ length N ]
[ eee on|off ]
[ advertise %x ]
[ tx-lpi on|off ]
[ tx-timer %d ]
hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE) software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE) hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE) software-receive (SOF_TIMESTAMPING_RX_SOFTWARE) software-system-clock (SOF_TIMESTAMPING_SOFTWARE) hardware-legacy-clock (SOF_TIMESTAMPING_SYS_HARDWARE) hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE) off (HWTSTAMP_TX_OFF) on (HWTSTAMP_TX_ON) one-step-sync (HWTSTAMP_TX_ONESTEP_SYNC) none (HWTSTAMP_FILTER_NONE) all (HWTSTAMP_FILTER_ALL) some (HWTSTAMP_FILTER_SOME) ptpv1-l4-event (HWTSTAMP_FILTER_PTP_V1_L4_EVENT) ptpv1-l4-sync (HWTSTAMP_FILTER_PTP_V1_L4_SYNC) ptpv1-l4-delay-req (HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) ptpv2-l4-event (HWTSTAMP_FILTER_PTP_V2_L4_EVENT) ptpv2-l4-sync (HWTSTAMP_FILTER_PTP_V2_L4_SYNC) ptpv2-l4-delay-req (HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) ptpv2-l2-event (HWTSTAMP_FILTER_PTP_V2_L2_EVENT) ptpv2-l2-sync (HWTSTAMP_FILTER_PTP_V2_L2_SYNC) ptpv2-l2-delay-req (HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) ptpv2-event (HWTSTAMP_FILTER_PTP_V2_EVENT) ptpv2-sync (HWTSTAMP_FILTER_PTP_V2_SYNC) ptpv2-delay-req (HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) I@ K@ {K@ ^K@ AK@ $K@ K@ J@ J@ AK@ AK@ J@ J@ N@ M@ N@ M@ M@ M@ M@ M@ M@ N@ N@ M@ M@ M@ N@ N@ N@ M@ 0N@ [@ Z@ \@ \@ {\@ U\@ ,\@ \@ [@ [@ `[@ %[@ @ @ H@ @ H@ H@ @ H@ H@ H@ H@ H@ @ H@ H@ @ H@ H@ @ H@ ʊ@ A ~@ A A A ;@ A /A }@ :A A LA p9@ _A uA v@ A @A A 8@ A æA t@ ѦA A (A 7@ PA A o@ A A A 4@ %A =A @l@ PA A cA Pi@ tA A A f@ A A A 4@ ŧA ߧA PT@ HA A A 1@ A A A 0@ !A A 0H@ A 8A A L@ A A 9A p-@ @A `A *@ A QA T@ A A lA P)@ 0A xA wA (@ A A p&@ A A A Q@ ϨA A A %@ A A pd@ $A A 1A $@ CA WA b@ hA zA A _@ @A hA A ` @ A ©A ]@ ̩A A ݩA @ A A @ A A !A .A 1024 B) count) 0x%08X
0x040F0: MPTC (Multicast packets tx count) 0x%08X
0x040F4: BPTC (Broadcast packets tx count) 0x%08X
0x040F8: TSCTC (TCP segment context tx count) 0x%08X
0x04104: RPTHC (Rx packets to host count) 0x%08X
0x04118: HGPTC (Host good packets tx count) 0x%08X
0x04128: HGORCL (Host good octets rx cnt lower) 0x%08X
0x0412C: HGORCH (Host good octets rx cnt upper) 0x%08X
0x04130: HGOTCL (Host good octets tx cnt lower) 0x%08X
0x04134: HGOTCH (Host good octets tx cnt upper) 0x%08X
0x04138: LENNERS (Length error count) 0x%08X
0x04228: SCVPC (SerDes/SGMII code viol pkt cnt) 0x%08X
0x0A018: HRMPC (Header redir missed pkt count) 0x%08X
0x0%02X: SRRCTL%d (Split and replic rx ctl%d) 0x%08X
0x0%02X: PSRTYPE%d (Packet split receive type%d) 0x%08X
0x0%02X: RDBAL%d (Rx desc base addr low%d) 0x%08X
0x0%02X: RDBAH%d (Rx desc base addr high%d) 0x%08X
0x0%02X: RDLEN%d (Rx descriptor length%d) 0x%08X
0x0%02X: RDH%d (Rx descriptor head%d) 0x%08X
0x0%02X: RDT%d (Rx descriptor tail%d) 0x%08X
0x0%02X: RXDCTL%d (Rx descriptor control%d) 0x%08X
0x0%02X: EITR%d (Interrupt throttle%d) 0x%08X
0x0%02X: IMIR%d (Immediate interrupt Rx%d) 0x%08X
0x0%02X: IMIREXT%d (Immediate interr Rx extended%d) 0x%08X
0x0%02X: RAL%02d (Receive address low%02d) 0x%08X
0x0%02X: RAH%02d (Receive address high%02d) 0x%08X
0x0%02X: TDBAL%d (Tx desc base address low%d) 0x%08X
0x0%02X: TDBAH%d (Tx desc base address high%d) 0x%08X
0x0%02X: TDLEN%d (Tx descriptor length%d) 0x%08X
0x0%02X: TDH%d (Transmit descriptor head%d) 0x%08X
0x0%02X: TDT%d (Transmit descriptor tail%d) 0x%08X
0x0%02X: TXDCTL%d (Transmit descriptor control%d) 0x%08X
0x0%02X: TDWBAL%d (Tx desc complete wb addr low%d) 0x%08X
0x0%02X: TDWBAH%d (Tx desc complete wb addr hi%d) 0x%08X
0x0%02X: DCA_TXCTRL%d (Tx DCA control%d) 0x%08X
0x0%02X: IP4AT%d (IPv4 address table%d) 0x%08X
0x0%02X: IP6AT%d (IPv6 address table%d) 0x%08X
0x0%02X: WUPM%02d (Wake up packet memory%02d) 0x%08X
0x0%02X: FFMT%03d (Flexible filter mask table%03d) 0x%08X
0x0%02X: FFVT%03d (Flexible filter value table%03d) 0x%08X
0x0%02X: FFLT%d (Flexible filter length table%d) 0x%08X
0x03410: TDFH (Tx data FIFO head) 0x%08X
0x03418: TDFT (Tx data FIFO tail) 0x%08X
0x03420: TDFHS (Tx data FIFO head saved) 0x%08X
0x03430: TDFPC (Tx data FIFO packet count) 0x%08X
0x%04lx: %-16s 0x%08x
addr_low addr_high hash_table_high hash_table_low r_des_start x_des_start r_buff_size ecntrl ievent imask ivec r_des_active x_des_active mii_data mii_speed r_bound r_fstart x_fstart fun_code r_cntrl r_hash x_cntrl MAL%d Registers
TX| CTP%d = 0x%08x
RX| EMAC%d Registers
IPCR = 0x%08x
ZMII%d Registers
RGMII%d Registers
FER = %08x SSR = %08x
TAH%d Registers
RCBS%d = 0x%08x (%d) CFG = 0x%08x ESR = 0x%08x IER = 0x%08x
TX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x
RX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x
MR0 = 0x%08x MR1 = 0x%08x RMR = 0x%08x
ISR = 0x%08x ISER = 0x%08x
TMR0 = 0x%08x TMR1 = 0x%08x
TRTR = 0x%08x RWMR = 0x%08x
IAR = %04x%08x
LSA = %04x%08x
IAHT = 0x%04x 0x%04x 0x%04x 0x%04x
GAHT = 0x%04x 0x%04x 0x%04x 0x%04x
VTPID = 0x%04x VTCI = 0x%04x
IPGVR = 0x%04x STACR = 0x%08x
OCTX = 0x%08x OCRX = 0x%08x
FER = %08x SSR = %08x
SMIISR = %08x
REVID = %08x MR = %08x TSR = %08x
SSR0 = %08x SSR1 = %08x SSR2 = %08x
SSR3 = %08x SSR4 = %08x SSR5 = %08x
0x00000: CTRL0 (Device control register) 0x%08X
Link reset: %s
VLAN mode: %s
0x00010: STATUS (Device status register) 0x%08X
Link up: %s
Bus type: %s
Bus speed: %s
Bus width: %s
0x00100: RCTL (Receive control register) 0x%08X
Receiver: %s
Store bad packets: %s
Unicast promiscuous: %s
Multicast promiscuous: %s
Descriptor minimum threshold size: %s
Broadcast accept mode: %s
VLAN filter: %s
Cononical form indicator: %s
0x00120: RDLEN (Receive desc length) 0x%08X
0x00128: RDH (Receive desc head) 0x%08X
0x00130: RDT (Receive desc tail) 0x%08X
0x00138: RDTR (Receive delay timer) 0x%08X
0x00600: TCTL (Transmit ctrl register) 0x%08X
Transmitter: %s
0x00610: TDLEN (Transmit desc length) 0x%08X
0x00618: TDH (Transmit desc head) 0x%08X
0x00620: TDT (Transmit desc tail) 0x%08X
0x00628: TIDV (Transmit delay timer) 0x%08X
1G 10G 0x042A4: LINKS (Link Status register) 0x%08X
Link Status: %s
Link Speed: %s
0x05080: FCTRL (Filter Control register) 0x%08X
Broadcast Accept: %s
Unicast Promiscuous: %s
Multicast Promiscuous: %s
Store Bad Packets: %s
Receive Flow Control Packets: %s
Receive Priority Flow Control Packets: %s
Discard Pause Frames: %s
Pass MAC Control Frames: %s
0x04294: MFLCN (TabMAC Flow Control register) 0x%08X
Receive Flow Control Packets: %s
Discard Pause Frames: %s
Pass MAC Control Frames: %s
Receive Priority Flow Control Packets: %s
0x05088: VLNCTRL (VLAN Control register) 0x%08X
VLAN Mode: %s
VLAN Filter: %s
0x02100: SRRCTL0 (Split and Replic Rx Control 0) 0x%08X
Receive Buffer Size: %uKB
0x03D00: RMCS (Receive Music Control register) 0x%08X
Transmit Flow Control: %s
Priority Flow Control: %s
0x04250: HLREG0 (Highlander Control 0 register) 0x%08X
Transmit CRC: %s
Receive CRC Strip: %s
Jumbo Frames: %s
Pad Short Frames: %s
Loopback: %s
0x00000: CTRL (Device Control) 0x%08X
0x00008: STATUS (Device Status) 0x%08X
0x00018: CTRL_EXT (Extended Device Control) 0x%08X
0x00020: ESDP (Extended SDP Control) 0x%08X
0x00028: EODSDP (Extended OD SDP Control) 0x%08X
0x00200: LEDCTL (LED Control) 0x%08X
0x00048: FRTIMER (Free Running Timer) 0x%08X
0x0004C: TCPTIMER (TCP Timer) 0x%08X
0x10010: EEC (EEPROM/Flash Control) 0x%08X
0x10014: EERD (EEPROM Read) 0x%08X
0x1001C: FLA (Flash Access) 0x%08X
0x10110: EEMNGCTL (Manageability EEPROM Control) 0x%08X
0x10114: EEMNGDATA (Manageability EEPROM R/W Data) 0x%08X
0x10110: FLMNGCTL (Manageability Flash Control) 0x%08X
0x1011C: FLMNGDATA (Manageability Flash Read Data) 0x%08X
0x10120: FLMNGCNT (Manageability Flash Read Count) 0x%08X
0x1013C: FLOP (Flash Opcode) 0x%08X
0x10200: GRC (General Receive Control) 0x%08X
0x00800: EICR (Extended Interrupt Cause) 0x%08X
0x00808: EICS (Extended Interrupt Cause Set) 0x%08X
0x00880: EIMS (Extended Interr. Mask Set/Read) 0x%08X
0x00888: EIMC (Extended Interrupt Mask Clear) 0x%08X
0x00810: EIAC (Extended Interrupt Auto Clear) 0x%08X
0x00890: EIAM (Extended Interr. Auto Mask EN) 0x%08X
0x00820: EITR0 (Extended Interrupt Throttle 0) 0x%08X
0x00900: IVAR0 (Interrupt Vector Allocation 0) 0x%08X
0x00000: MSIXT (MSI-X Table) 0x%08X
0x02000: MSIXPBA (MSI-X Pending Bit Array) 0x%08X
0x11068: PBACL (MSI-X PBA Clear) 0x%08X
0x00898: GPIE (General Purpose Interrupt EN) 0x%08X
0x03008: PFCTOP (Priority Flow Ctrl Type Opcode) 0x%08X
0x%05X: FCCTV%d (Flow Ctrl Tx Timer Value %d) 0x%08X
0x%05X: FCRTL%d (Flow Ctrl Rx Threshold low %d) 0x%08X
0x%05X: FCRTH%d (Flow Ctrl Rx Threshold High %d) 0x%08X
0x032A0: FCRTV (Flow Control Refresh Threshold) 0x%08X
0x0CE00: TFCS (Transmit Flow Control Status) 0x%08X
0x%05X: RDBAL%02d (Rx Desc Base Addr Low %02d) 0x%08X
0x%05X: RDBAH%02d (Rx Desc Base Addr High %02d) 0x%08X
0x%05X: RDLEN%02d (Receive Descriptor Length %02d) 0x%08X
0x%05X: RDH%02d (Receive Descriptor Head %02d) 0x%08X
0x%05X: RDT%02d (Receive Descriptor Tail %02d) 0x%08X
0x%05X: RXDCTL%02d (Receive Descriptor Control %02d) 0x%08X
0x%05X: SRRCTL%02d (Split and Replic Rx Control %02d) 0x%08X
0x%05X: DCA_RXCTRL%02d (Rx DCA Control %02d) 0x%08X
0x02F00: RDRXCTL (Receive DMA Control) 0x%08X
0x%05X: RXPBSIZE%d (Receive Packet Buffer Size %d) 0x%08X
0x03000: RXCTRL (Receive Control) 0x%08X
0x03D04: DROPEN (Drop Enable Control) 0x%08X
0x05000: RXCSUM (Receive Checksum Control) 0x%08X
0x05008: RFCTL (Receive Filter Control) 0x%08X
0x%05X: RAL%02d (Receive Address Low%02d) 0x%08X
0x%05X: RAH%02d (Receive Address High %02d) 0x%08X
0x05480: PSRTYPE (Packet Split Receive Type) 0x%08X
0x05090: MCSTCTRL (Multicast Control) 0x%08X
0x05818: MRQC (Multiple Rx Queues Command) 0x%08X
0x0581C: VMD_CTL (VMDq Control) 0x%08X
0x%05X: IMIR%d (Immediate Interrupt Rx %d) 0x%08X
0x%05X: IMIREXT%d (Immed. Interr. Rx Extended %d) 0x%08X
0x05AC0: IMIRVP (Immed. Interr. Rx VLAN Prior.) 0x%08X
0x%05X: TDBAL%02d (Tx Desc Base Addr Low %02d) 0x%08X
0x%05X: TDBAH%02d (Tx Desc Base Addr High %02d) 0x%08X
0x%05X: TDLEN%02d (Tx Descriptor Length %02d) 0x%08X
0x%05X: TDH%02d (Transmit Descriptor Head %02d) 0x%08X
0x%05X: TDT%02d (Transmit Descriptor Tail %02d) 0x%08X
0x%05X: TXDCTL%02d (Tx Descriptor Control %02d) 0x%08X
0x%05X: TDWBAL%02d (Tx Desc Compl. WB Addr low %02d) 0x%08X
0x%05X: TDWBAH%02d (Tx Desc Compl. WB Addr High %02d) 0x%08X
0x07E00: DTXCTL (DMA Tx Control) 0x%08X
0x%05X: DCA_TXCTRL%02d (Tx DCA Control %02d) 0x%08X
0x0CB00: TIPG (Transmit IPG Control) 0x%08X
0x%05X: TXPBSIZE%d (Transmit Packet Buffer Size %d) 0x%08X
0x0CD10: MNGTXMAP (Manageability Tx TC Mapping) 0x%08X
0x05800: WUC (Wake up Control) 0x%08X
0x05808: WUFC (Wake Up Filter Control) 0x%08X
0x05810: WUS (Wake Up Status) 0x%08X
0x05838: IPAV (IP Address Valid) 0x%08X
0x05840: IP4AT (IPv4 Address Table) 0x%08X
0x05880: IP6AT (IPv6 Address Table) 0x%08X
0x05900: WUPL (Wake Up Packet Length) 0x%08X
0x05A00: WUPM (Wake Up Packet Memory) 0x%08X
0x09000: FHFT (Flexible Host Filter Table) 0x%08X
0x07F40: DPMCS (Desc. Plan Music Ctrl Status) 0x%08X
0x0CD00: PDPMCS (Pkt Data Plan Music ctrl Stat) 0x%08X
0x050A0: RUPPBMR (Rx User Prior to Pkt Buff Map) 0x%08X
0x%05X: RT2CR%d (Receive T2 Configure %d) 0x%08X
0x%05X: RT2SR%d (Recieve T2 Status %d) 0x%08X
0x%05X: TDTQ2TCCR%d (Tx Desc TQ2 TC Config %d) 0x%08X
0x%05X: TDTQ2TCSR%d (Tx Desc TQ2 TC Status %d) 0x%08X
0x%05X: TDPT2TCCR%d (Tx Data Plane T2 TC Config %d) 0x%08X
0x%05X: TDPT2TCSR%d (Tx Data Plane T2 TC Status %d) 0x%08X
0x04000: crcerrs (CRC Error Count) 0x%08X
0x04004: illerrc (Illegal Byte Error Count) 0x%08X
0x04008: errbc (Error Byte Count) 0x%08X
0x04010: mspdc (MAC Short Packet Discard Count) 0x%08X
0x%05X: mpc%d (Missed Packets Count %d) 0x%08X
0x04034: mlfc (MAC Local Fault Count) 0x%08X
0x04038: mrfc (MAC Remote Fault Count) 0x%08X
0x04040: rlec (Receive Length Error Count) 0x%08X
0x03F60: lxontxc (Link XON Transmitted Count) 0x%08X
0x0CF60: lxonrxc (Link XON Received Count) 0x%08X
0x03F68: lxofftxc (Link XOFF Transmitted Count) 0x%08X
0x0CF68: lxoffrxc (Link XOFF Received Count) 0x%08X
0x%05X: pxontxc%d (Priority XON Tx Count %d) 0x%08X
0x%05X: pxonrxc%d (Priority XON Received Count %d) 0x%08X
0x%05X: pxofftxc%d (Priority XOFF Tx Count %d) 0x%08X
0x%05X: pxoffrxc%d (Priority XOFF Received Count %d) 0x%08X
0x0405C: prc64 (Packets Received (64B) Count) 0x%08X
0x04060: prc127 (Packets Rx (65-127B) Count) 0x%08X
0x04064: prc255 (Packets Rx (128-255B) Count) 0x%08X
0x04068: prc511 (Packets Rx (256-511B) Count) 0x%08X
0x0406C: prc1023 (Packets Rx (512-1023B) Count) 0x%08X
0x04070: prc1522 (Packets Rx (1024-Max) Count) 0x%08X
0x04074: gprc (Good Packets Received Count) 0x%08X
0x04078: bprc (Broadcast Packets Rx Count) 0x%08X
0x0407C: mprc (Multicast Packets Rx Count) 0x%08X
0x04080: gptc (Good Packets Transmitted Count) 0x%08X
0x04088: gorcl (Good Octets Rx Count Low) 0x%08X
0x0408C: gorch (Good Octets Rx Count High) 0x%08X
0x04090: gotcl (Good Octets Tx Count Low) 0x%08X
0x04094: gotch (Good Octets Tx Count High) 0x%08X
0x%05X: rnbc%d (Receive No Buffers Count %d) 0x%08X
0x040A4: ruc (Receive Undersize count) 0x%08X
0x040A8: rfc (Receive Fragment Count) 0x%08X
0x040AC: roc (Receive Oversize Count) 0x%08X
0x040B0: rjc (Receive Jabber Count) 0x%08X
0x040B4: mngprc (Management Packets Rx Count) 0x%08X
0x040B8: mngpdc (Management Pkts Dropped Count) 0x%08X
0x0CF90: mngptc (Management Packets Tx Count) 0x%08X
0x040C0: torl (Total Octets Rx Count Low) 0x%08X
0x040C4: torh (Total Octets Rx Count High) 0x%08X
0x040D0: tpr (Total Packets Received) 0x%08X
0x040D4: tpt (Total Packets Transmitted) 0x%08X
0x040D8: ptc64 (Packets Tx (64B) Count) 0x%08X
0x040DC: ptc127 (Packets Tx (65-127B) Count) 0x%08X
0x040E0: ptc255 (Packets Tx (128-255B) Count) 0x%08X
0x040E4: ptc511 (Packets Tx (256-511B) Count) 0x%08X
0x040E8: ptc1023 (Packets Tx (512-1023B) Count) 0x%08X
0x040EC: ptc1522 (Packets Tx (1024-Max) Count) 0x%08X
0x040F0: mptc (Multicast Packets Tx Count) 0x%08X
0x040F4: bptc (Broadcast Packets Tx Count) 0x%08X
0x04120: xec (XSUM Error Count) 0x%08X
0x%05X: qprc%02d (Queue Packets Rx Count %02d) 0x%08X
0x%05X: qptc%02d (Queue Packets Tx Count %02d) 0x%08X
0x%05X: qbrc%02d (Queue Bytes Rx Count %02d) 0x%08X
0x%05X: qbtc%02d (Queue Bytes Tx Count %02d) 0x%08X
0x04200: PCS1GCFIG (PCS_1G Gloabal Config 1) 0x%08X
0x04208: PCS1GLCTL (PCS_1G Link Control) 0x%08X
0x0420C: PCS1GLSTA (PCS_1G Link Status) 0x%08X
0x04210: PCS1GDBG0 (PCS_1G Debug 0) 0x%08X
0x04214: PCS1GDBG1 (PCS_1G Debug 1) 0x%08X
0x04218: PCS1GANA (PCS-1G Auto Neg. Adv.) 0x%08X
0x0421C: PCS1GANLP (PCS-1G AN LP Ability) 0x%08X
0x04220: PCS1GANNP (PCS_1G Auto Neg Next Page Tx) 0x%08X
0x04224: PCS1GANLPNP (PCS_1G Auto Neg LPs Next Page) 0x%08X
0x04244: HLREG1 (Highlander Status 1) 0x%08X
0x04248: PAP (Pause and Pace) 0x%08X
0x0424C: MACA (MDI Auto-Scan Command and Addr) 0x%08X
0x04250: APAE (Auto-Scan PHY Address Enable) 0x%08X
0x04254: ARD (Auto-Scan Read Data) 0x%08X
0x04258: AIS (Auto-Scan Interrupt Status) 0x%08X
0x0425C: MSCA (MDI Single Command and Addr) 0x%08X
0x04260: MSRWD (MDI Single Read and Write Data) 0x%08X
0x04264: MLADD (MAC Address Low) 0x%08X
0x04268: MHADD (MAC Addr High/Max Frame size) 0x%08X
0x0426C: TREG (Test Register) 0x%08X
0x04288: PCSS1 (XGXS Status 1) 0x%08X
0x0428C: PCSS2 (XGXS Status 2) 0x%08X
0x04290: XPCSS (10GBASE-X PCS Status) 0x%08X
0x04298: SERDESC (SERDES Interface Control) 0x%08X
0x0429C: MACS (FIFO Status/CNTL Report) 0x%08X
0x042A0: AUTOC (Auto Negotiation Control) 0x%08X
0x042A8: AUTOC2 (Auto Negotiation Control 2) 0x%08X
0x042AC: AUTOC3 (Auto Negotiation Control 3) 0x%08X
0x042B0: ANLP1 (Auto Neg Lnk Part. Ctrl Word 1) 0x%08X
0x042B0: ANLP2 (Auto Neg Lnk Part. Ctrl Word 2) 0x%08X
0x04800: ATLASCTL (Atlas Analog Configuration) 0x%08X
0x02C20: RDSTATCTL (Rx DMA Statistic Control) 0x%08X
0x%05X: RDSTAT%d (Rx DMA Statistics %d) 0x%08X
0x02F08: RDHMPN (Rx Desc Handler Mem Page num) 0x%08X
0x02F10: RIC_DW0 (Rx Desc Hand. Mem Read Data 0) 0x%08X
0x02F14: RIC_DW1 (Rx Desc Hand. Mem Read Data 1) 0x%08X
0x02F18: RIC_DW2 (Rx Desc Hand. Mem Read Data 2) 0x%08X
0x02F1C: RIC_DW3 (Rx Desc Hand. Mem Read Data 3) 0x%08X
0x02F20: RDPROBE (Rx Probe Mode Status) 0x%08X
0x07C20: TDSTATCTL (Tx DMA Statistic Control) 0x%08X
0x%05X: TDSTAT%d (Tx DMA Statistics %d) 0x%08X
0x07F08: TDHMPN (Tx Desc Handler Mem Page Num) 0x%08X
0x07F10: TIC_DW0 (Tx Desc Hand. Mem Read Data 0) 0x%08X
0x07F14: TIC_DW1 (Tx Desc Hand. Mem Read Data 1) 0x%08X
0x07F18: TIC_DW2 (Tx Desc Hand. Mem Read Data 2) 0x%08X
0x07F1C: TIC_DW3 (Tx Desc Hand. Mem Read Data 3) 0x%08X
0x07F20: TDPROBE (Tx Probe Mode Status) 0x%08X
0x0C600: TXBUFCTRL (TX Buffer Access Control) 0x%08X
0x0C610: TXBUFDATA0 (TX Buffer DATA 0) 0x%08X
0x0C614: TXBUFDATA1 (TX Buffer DATA 1) 0x%08X
0x0C618: TXBUFDATA2 (TX Buffer DATA 2) 0x%08X
0x0C61C: TXBUFDATA3 (TX Buffer DATA 3) 0x%08X
0x03600: RXBUFCTRL (RX Buffer Access Control) 0x%08X
0x03610: RXBUFDATA0 (RX Buffer DATA 0) 0x%08X
0x03614: RXBUFDATA1 (RX Buffer DATA 1) 0x%08X
0x03618: RXBUFDATA2 (RX Buffer DATA 2) 0x%08X
0x0361C: RXBUFDATA3 (RX Buffer DATA 3) 0x%08X
0x%05X: PCIE_DIAG%d (PCIe Diagnostic %d) 0x%08X
0x050A4: RFVAL (Receive Filter Validation) 0x%08X
0x042B8: MDFTC1 (MAC DFT Control 1) 0x%08X
0x042C0: MDFTC2 (MAC DFT Control 2) 0x%08X
0x042C4: MDFTFIFO1 (MAC DFT FIFO 1) 0x%08X
0x042C8: MDFTFIFO2 (MAC DFT FIFO 2) 0x%08X
0x042CC: MDFTS (MAC DFT Status) 0x%08X
0x1106C: PCIEECCCTL (PCIe ECC Control) 0x%08X
0x0C300: PBTXECC (Packet Buffer Tx ECC) 0x%08X
0x03300: PBRXECC (Packet Buffer Rx ECC) 0x%08X
Magic number 0x%08x does not match 0x%08x
0x00: CR (Command): 0x%08x
Transmit %s
Receive %s
0x04: CFG (Configuration): 0x%08x
%s Endian
Boot ROM %s
Internal Phy %s
Phy Reset %s
External Phy %s
Default Auto-Negotiation %s, %s %s Mb %s Duplex
Phy Interrupt %sAuto-Cleared
Phy Configuration = 0x%02x
Auto-Negotiation %s
%s Polarity
%s Duplex
%d Mb/s
Link %s
0x08: MEAR (EEPROM Access): 0x%08x
0x0c: PTSCR (PCI Test Control): 0x%08x
EEPROM Self Test %s
Rx Filter Self Test %s
Tx FIFO Self Test %s
Rx FIFO Self Test %s
EEPROM Reload In Progress
0x10: ISR (Interrupt Status): 0x%08x
0x14: IMR (Interrupt Mask): 0x%08x
0x18: IER (Interrupt Enable): 0x%08x
0x20: TXDP (Tx Descriptor Pointer): 0x%08x
0x24: TXCFG (Tx Config): 0x%08x
Drain Threshhold = %d bytes (%d)
Fill Threshhold = %d bytes (%d)
Max DMA Burst per Tx = %d bytes
Automatic Tx Padding %s
Mac Loopback %s
Heartbeat Ignore %s
Carrier Sense Ignore %s
0x30: RXDP (Rx Descriptor Pointer): 0x%08x
0x34: RXCFG (Rx Config): 0x%08x
Drain Threshhold = %d bytes (%d)
Max DMA Burst per Rx = %d bytes
Long Packets %s
Tx Packets %s
Runt Packets %s
Error Packets %s
0x3c: CCSR (CLKRUN Control/Status): 0x%08x
CLKRUNN %s
Power Management %s
Power Management Event Pending
0x40: WCSR (Wake-on-LAN Control/Status): 0x%08x
Wake on Phy Interrupt Enabled
Wake on Unicast Packet Enabled
Wake on Multicast Packet Enabled
Wake on Broadcast Packet Enabled
Wake on Pattern 0 Match Enabled
Wake on Pattern 1 Match Enabled
Wake on Pattern 2 Match Enabled
Wake on Pattern 3 Match Enabled
Wake on Magic Packet Enabled
Magic Packet SecureOn Enabled
Unicast Packet Received
Multicast Packet Received
Broadcast Packet Received
0x44: PCR (Pause Control/Status): 0x%08x
Pause Counter = %d
Pause %sNegotiated
Pause on DA %s
Pause on Mulitcast %s
Pause %s
PS_RCVD: Pause Frame Received
0x48: RFCR (Rx Filter Control): 0x%08x
Unicast Hash %s
Multicast Hash %s
Arp %s
Pattern 0 Match %s
Pattern 1 Match %s
Pattern 2 Match %s
Pattern 3 Match %s
Perfect Match %s
All Unicast %s
All Multicast %s
All Broadcast %s
Rx Filter %s
0x4c: RFDR (Rx Filter Data): 0x%08x
PMATCH 1-0 = 0x%08x
PMATCH 3-2 = 0x%08x
PMATCH 5-4 = 0x%08x
PCOUNT 1-0 = 0x%08x
PCOUNT 3-2 = 0x%08x
SOPASS 1-0 = 0x%08x
SOPASS 3-2 = 0x%08x
SOPASS 5-4 = 0x%08x
0x50: BRAR (Boot ROM Address): 0x%08x
Automatically Increment Address
0x54: BRDR (Boot ROM Data): 0x%08x
0x58: SRR (Silicon Revision): 0x%08x
0x5c: MIBC (Mgmt Info Base Control): 0x%08x
Counter Overflow Warning
0x60: MIB[0] (Rx Errored Packets): 0x%04x
0x64: MIB[1] (Rx Frame Sequence Errors): 0x%02x
0x68: MIB[2] (Rx Missed Packets): 0x%02x
0x6c: MIB[3] (Rx Alignment Errors): 0x%02x
0x70: MIB[4] (Rx Symbol Errors): 0x%02x
0x74: MIB[5] (Rx Long Frame Errors): 0x%02x
0x78: MIB[6] (Tx Heartbeat Errors): 0x%02x
0x80: BMCR (Basic Mode Control): 0x%04x
%s Duplex
Port is Powered %s
Auto-Negotiation %s
%d Mb/s
Auto-Negotiation Restarting
0x84: BMSR (Basic Mode Status): 0x%04x
Link %s
%sCapable of Auto-Negotiation
Auto-Negotiation %sComplete
%sCapable of Preamble Suppression
%sCapable of 10Base-T Half Duplex
%sCapable of 10Base-T Full Duplex
%sCapable of 100Base-TX Half Duplex
%sCapable of 100Base-TX Full Duplex
%sCapable of 100Base-T4
Jabber Condition Detected
0x88: PHYIDR1 (PHY ID #1): 0x%04x
0x8c: PHYIDR2 (PHY ID #2): 0x%04x
OUI = 0x%06x
Model = 0x%02x (%d)
Revision = 0x%01x (%d)
0x90: ANAR (Autoneg Advertising): 0x%04x
Protocol Selector = 0x%02x (%d)
Advertising 10Base-T Half Duplex
Advertising 10Base-T Full Duplex
Advertising 100Base-TX Half Duplex
Advertising 100Base-TX Full Duplex
Indicating Remote Fault
0x94: ANLPAR (Autoneg Partner): 0x%04x
Supports 10Base-T Half Duplex
Supports 10Base-T Full Duplex
Supports 100Base-TX Half Duplex
Supports 100Base-TX Full Duplex
Indicates Acknowledgement
0x98: ANER (Autoneg Expansion): 0x%04x
Link Partner Can %sAuto-Negotiate
Link Code Word %sReceived
Next Page %sSupported
Link Partner Next Page %sSupported
Parallel Detection Fault
0x9c: ANNPTR (Autoneg Next Page Tx): 0x%04x
0xc0: PHYSTS (Phy Status): 0x%04x
Link %s
%d Mb/s
%s Duplex
Auto-Negotiation %sComplete
%s Polarity
0xc4: MICR (MII Interrupt Control): 0x%04x
0xc8: MISR (MII Interrupt Status): 0x%04x
Rx Error Counter Half-Full Interrupt %s
False Carrier Counter Half-Full Interrupt %s
Auto-Negotiation Complete Interrupt %s
Remote Fault Interrupt %s
Jabber Interrupt %s
Link Change Interrupt %s
0xcc: PGSEL (Phy Register Page Select): 0x%04x
0xd0: FCSCR (False Carrier Counter): 0x%04x
0xd4: RECR (Rx Error Counter): 0x%04x
0xd8: PCSR (100Mb/s PCS Config/Status): 0x%04x
NRZI Bypass %s
%s Signal Detect Algorithm
%s Signal Detect Operation
True Quiet Mode %s
Rx Clock is %s
4B/5B Operation %s
Forced 100 Mb/s Good Link
0xe4: PHYCR (Phy Control): 0x%04x
Phy Address = 0x%x (%d)
%sPause Compatible with Link Partner
LED Stretching %s
Phy Self Test %s
Self Test Sequence = PSR%d
0xe8: TBTSCR (10Base-T Status/Control): 0x%04x
Jabber %s
Heartbeat %s
Polarity Auto-Sense/Correct %s
%s Polarity %s
Normal Link Pulse %s
10 Mb/s Loopback %s
Forced 10 Mb/s Good Link
0xe4: PMDCSR: 0x%04x
0xf4: DSPCFG: 0x%04x
0xf8: SDCFG: 0x%04x
0xfc: TSTDAT: 0x%04x
Address Data
------- ------
0x%02x 0x%04x
%s Interrupt: %s
Mac/BIU Registers
Active Reset In Progress
Normal Reversed Not Done Not Half/Full 10/100 Advertise In Progress Passed Failed Rx Complete Rx Descriptor Rx Packet Error Rx Early Threshold Rx Idle Rx Overrun Tx Packet OK Tx Descriptor Tx Packet Error Tx Idle Tx Underrun MIB Service Software Power Management Event Phy High Bits Error Rx Status FIFO Overrun Received Target Abort Received Master Abort Signaled System Error Detected Parity Error Rx Reset Complete Tx Reset Complete No Interrupts Active
Masked Interrupts %s
Rejected Accepted Wake on Arp Enabled
SecureOn Hack Detected
Phy Interrupt Received
Arp Received
Pattern 0 Received
Pattern 1 Received
Pattern 2 Received
Pattern 3 Received
Magic Packet Received
Counters Frozen
Value = %d
Internal Phy Registers
----------------------
Port Isolated
Loopback Enabled
Remote Fault Detected
Advertising 100Base-T4
Advertising Pause
Next Page Desired
Supports 100Base-T4
Supports Pause
Indicates Remote Fault
Reverse MII Interrupt Detected
False Carrier Detected
Rx Error Detected
MII Interrupts %s
MII Interrupt Pending
Bypassed Phase-Adjusted Free-Running Forced Reduced Enhanced Failed or Not Run 'Magic' Phy Registers
Force Detected Driver: %s
Version: %s
APROM: %04x CSR%02d: BCR%02d: MII%02d: BABL CERR MISS MERR RINT IDON INTR RXON TXON TDMD STOP INIT BABLM MISSM MERRM RINTM TINTM IDONM DXSUFLO LAPPEN DXMT2PD EMBA BSWP EN124 DMAPLUS TXDPOLL APAD_XMT ASTRP_RCV MFCO MFCON UINTCMD UINT RCVCCO RCVCCOM TXSTRT TXSTRTM JAB JABM TOKINTD LTINTEN SINT SINTE SLPINT SLPINTE EXDINT EXDINTE MPPLBA MPINT MPINTE MPEN MPMODE SPND FASTSPNDE RXFRTG RDMD RXDPOLL STINT STINTE MREINT MREINTE MAPINT MAPINTE MCCINT MCCINTE MCCIINT MCCIINTE MIIPDTINT MIIPDTINTE PCnet/PCI 79C970
PCnet/PCI II 79C970A
PCnet/FAST 79C971
PCnet/FAST+ 79C972
PCnet/FAST III 79C973
PCnet/Home 79C978
PCnet/FAST III 79C975
PCnet/PRO 79C976
VER: %04x PARTIDU: %04x
TMAULOOP LEDPE APROMWE INTLEVEL EADISEL AWAKE ASEL XMAUSEL PVALID EEDET CSR0: Status and Control 0x%04x
CSR3: Interrupt Mask 0x%04x
CSR4: Test and Features 0x%04x
CSR5: Ext Control and Int 1 0x%04x
CSR7: Ext Control and Int 2 0x%04x
CSR15: Mode 0x%04x
CSR40: Current RX Byte Count 0x%04x
CSR41: Current RX Status 0x%04x
CSR42: Current TX Byte Count 0x%04x
CSR43: Current TX Status 0x%04x
CSR88: Chip ID Lower 0x%04x
CSR89: Chip ID Upper 0x%04x
CSR112: Missed Frame Count 0x%04x
CSR114: RX Collision Count 0x%04x
BCR2: Misc. Configuration 0x%04x
BCR9: Full-Duplex Control 0x%04x
BCR18: Burst and Bus Control 0x%04x
BCR19: EEPROM Control and Status 0x%04x
BCR23: PCI Subsystem Vendor ID 0x%04x
BCR24: PCI Subsystem ID 0x%04x
BCR31: Software Timer 0x%04x
BCR32: MII Control and Status 0x%04x
BCR35: PCI Vendor ID 0x%04x
RxErr TxErr RxNoBuf LinkChg RxFIFO TxNoBuf SWInt TimeOut SERR %s%s%s%s%s%s%s%s%s%s%s
ERxOK ERxOverWrite ERxBad ERxGood %s%s%s%s
, RESET Big-endian mode
Home LAN enable
VLAN de-tagging
RX checksumming
PCI 64-bit DAC
PCI Multiple RW
RTL-8139 RTL-8139-K RTL-8139A RTL-8139A-G RTL-8139B RTL-8130 RTL-8139C RTL-8100 RTL-8100B/8139D RTL-8139C+ RTL-8101 RTL-8169 RTL-8169S RTL-8110S RTL-8169/8110SB RTL-8169/8110SCd RTL-8169/8110SCe RTL-8168/8111Bb RTL-8168/8111Bef RTL-8101Ebc RTL-8100E(1) RTL-8100E(2) Unknown RealTek chip (mask: 0x%08x)
RealTek %s registers:
--------------------------------------------------------
0x00: MAC Address %02x:%02x:%02x:%02x:%02x:%02x
0x08: Multicast Address Filter 0x%08x 0x%08x
0x10: Dump Tally Counter Command 0x%08x 0x%08x
0x20: Tx Normal Priority Ring Addr 0x%08x 0x%08x
0x28: Tx High Priority Ring Addr 0x%08x 0x%08x
0x10: Transmit Status Desc 0 0x%08x
0x14: Transmit Status Desc 1 0x%08x
0x18: Transmit Status Desc 2 0x%08x
0x1C: Transmit Status Desc 3 0x%08x
0x20: Transmit Start Addr 0 0x%08x
0x24: Transmit Start Addr 1 0x%08x
0x28: Transmit Start Addr 2 0x%08x
0x2C: Transmit Start Addr 3 0x%08x
0x30: Flash memory read/write 0x%08x
0x30: Rx buffer addr (C mode) 0x%08x
0x34: Early Rx Byte Count %8u
0x36: Early Rx Status 0x%02x
0x37: Command 0x%02x
Rx %s, Tx %s%s
0x38: Current Address of Packet Read (C mode) 0x%04x
0x3A: Current Rx buffer address (C mode) 0x%04x
0x3C: Interrupt Mask 0x%04x
0x3E: Interrupt Status 0x%04x
0x40: Tx Configuration 0x%08x
0x44: Rx Configuration 0x%08x
0x48: Timer count 0x%08x
0x4C: Missed packet counter 0x%06x
0x50: EEPROM Command 0x%02x
0x51: Config 0 0x%02x
0x52: Config 1 0x%02x
0x53: Config 2 0x%02x
0x54: Config 3 0x%02x
0x55: Config 4 0x%02x
0x56: Config 5 0x%02x
0x58: Timer interrupt 0x%08x
0x5C: Multiple Interrupt Select 0x%04x
0x60: PHY access 0x%08x
0x54: Timer interrupt 0x%08x
0x58: Media status 0x%02x
0x59: Config 3 0x%02x
0x5A: Config 4 0x%02x
0x64: TBI control and status 0x%08x
0x68: TBI Autonegotiation advertisement (ANAR) 0x%04x
0x6A: TBI Link partner ability (LPAR) 0x%04x
0x6C: PHY status 0x%02x
0x84: PM wakeup frame 0 0x%08x 0x%08x
0x8C: PM wakeup frame 1 0x%08x 0x%08x
0x94: PM wakeup frame 2 (low) 0x%08x 0x%08x
0x9C: PM wakeup frame 2 (high) 0x%08x 0x%08x
0xA4: PM wakeup frame 3 (low) 0x%08x 0x%08x
0xAC: PM wakeup frame 3 (high) 0x%08x 0x%08x
0xB4: PM wakeup frame 4 (low) 0x%08x 0x%08x
0xBC: PM wakeup frame 4 (high) 0x%08x 0x%08x
0xC4: Wakeup frame 0 CRC 0x%04x
0xC6: Wakeup frame 1 CRC 0x%04x
0xC8: Wakeup frame 2 CRC 0x%04x
0xCA: Wakeup frame 3 CRC 0x%04x
0xCC: Wakeup frame 4 CRC 0x%04x
0xDA: RX packet maximum size 0x%04x
0x78: PHY parameter 1 0x%08x
0x7C: Twister parameter 0x%08x
0x80: PHY parameter 2 0x%02x
0x82: Low addr of a Tx Desc w/ Tx DMA OK 0x%04x
0x82: MII register 0x%02x
0x84: PM CRC for wakeup frame 0 0x%02x
0x85: PM CRC for wakeup frame 1 0x%02x
0x86: PM CRC for wakeup frame 2 0x%02x
0x87: PM CRC for wakeup frame 3 0x%02x
0x88: PM CRC for wakeup frame 4 0x%02x
0x89: PM CRC for wakeup frame 5 0x%02x
0x8A: PM CRC for wakeup frame 6 0x%02x
0x8B: PM CRC for wakeup frame 7 0x%02x
0x8C: PM wakeup frame 0 0x%08x 0x%08x
0x94: PM wakeup frame 1 0x%08x 0x%08x
0x9C: PM wakeup frame 2 0x%08x 0x%08x
0xA4: PM wakeup frame 3 0x%08x 0x%08x
0xAC: PM wakeup frame 4 0x%08x 0x%08x
0xB4: PM wakeup frame 5 0x%08x 0x%08x
0xBC: PM wakeup frame 6 0x%08x 0x%08x
0xC4: PM wakeup frame 7 0x%08x 0x%08x
0xCC: PM LSB CRC for wakeup frame 0 0x%02x
0xCD: PM LSB CRC for wakeup frame 1 0x%02x
0xCE: PM LSB CRC for wakeup frame 2 0x%02x
0xCF: PM LSB CRC for wakeup frame 3 0x%02x
0xD0: PM LSB CRC for wakeup frame 4 0x%02x
0xD1: PM LSB CRC for wakeup frame 5 0x%02x
0xD2: PM LSB CRC for wakeup frame 6 0x%02x
0xD3: PM LSB CRC for wakeup frame 7 0x%02x
0xD4: Flash memory read/write 0x%08x
0xD8: Config 5 0x%02x
0xE0: C+ Command 0x%04x
0xE2: Interrupt Mitigation 0x%04x
TxTimer: %u
TxPackets: %u
RxTimer: %u
RxPackets: %u
0xE4: Rx Ring Addr 0x%08x 0x%08x
0xEC: Early Tx threshold 0x%02x
0xFC: External MII register 0x%08x
0xF0: Func Event 0x%08x
0xF4: Func Event Mask 0x%08x
0xF8: Func Preset State 0x%08x
0xFC: Func Force Event 0x%08x
0x5E: PCI revision id 0x%02x
0x60: Transmit Status of All Desc (C mode) 0x%04x
0x62: MII Basic Mode Control Register 0x%04x
0x64: MII Basic Mode Status Register 0x%04x
0x66: MII Autonegotiation Advertising 0x%04x
0x68: MII Link Partner Ability 0x%04x
0x6A: MII Expansion 0x%04x
0x6C: MII Disconnect counter 0x%04x
0x6E: MII False carrier sense counter 0x%04x
0x70: MII Nway test 0x%04x
0x72: MII RX_ER counter 0x%04x
0x74: MII CS configuration 0x%04x
Address Data
---------- ----
0x%08x 0x%02x
Offset Value
------ ----------
0x%04x 0x%08x
PCI config
----------
%02x Addr %d %02X%c
MAC Addresses
Genesis Yukon Yukon-Lite Yukon-LP Yukon-2 XL Yukon Extreme Yukon-2 EC Ultra Yukon-2 EC Yukon-2 FE Yukon-2 FE Plus Yukon Supreme Yukon Ultra 2 Yukon Optima (Unknown) (rev %d)
%s Prefetch
Control 0x%08X
Last Index %u
TX1 report %u
TX2 report %u
TX threshold %u
Put Index %u
Get Index %u
Init 0x%08X Value 0x%08X
Control Registers
Moderation Timer
%s (disabled)
%s
%12s address: %02X %02X Physical %-32s 0x%08X
Bus Management Unit
Status Receive 1 Transmit 1 Receive 2 Transmit 2
Status FIFO
Status level TX status ISR Rx GMAC 1 Tx GMAC 1 Receive Queue 1 Sync Transmit Queue 1 Async Transmit Queue 1 Receive RAMbuffer 1 Sync Transmit RAMbuffer 1 Async Transmit RAMbuffer 1 Receive RAMbuffer 2 Sync Transmit RAMbuffer 2 Async Transmit RAMbuffer 21 Rx GMAC 2 Tx GMAC 2 Blink Source Receive MAC FIFO 1 Transmit MAC FIFO 1 Receive Queue 2 Async Transmit Queue 2 Sync Transmit Queue 2 Receive MAC FIFO 2 Transmit MAC FIFO 2 Descriptor Poll End Address Almost Full Thresh Control/Test FIFO Flush Mask FIFO Flush Threshold Truncation Threshold Upper Pause Threshold Lower Pause Threshold VLAN Tag FIFO Write Pointer FIFO Write Level FIFO Read Pointer FIFO Read Level Connector type 0x%02X (%c)
PMD type 0x%02X (%c)
PHY type 0x%02X
Chip Id 0x%02X Ram Buffer 0x%02X
Start Address 0x%08x%08x
Test 0x%02X Control 0x%02X
Register Access Port 0x%02X
LED Control/Status 0x%08X
Interrupt Source 0x%08X
Interrupt Mask 0x%08X
Interrupt Hardware Error Source 0x%08X
Interrupt Hardware Error Mask 0x%08X
Interrupt Control 0x%08X
Interrupt Moderation Mask 0x%08X
Hardware Moderation Mask 0x%08X
General Purpose I/O 0x%08X
Descriptor Address 0x%08X%08X
Address Counter 0x%08X%08X
Current Byte Counter %d
BMU Control/Status 0x%08X
Flag & FIFO Address 0x%08X
Control 0x%08X
Next 0x%08X
Data 0x%08X%08X
Status 0x%08X
Timestamp 0x%08X
Csum1 Offset %4d Position %d
Csum2 Offset %4d Position %d
Csum Start 0x%04X Pos %4d Write %d
Buffer control 0x%04X
Byte Counter %d
Descriptor Address 0x%08X%08X
Done 0x%04X
Request 0x%08X%08X
Start Address 0x%08X
End Address 0x%08X
Write Pointer 0x%08X
Read Pointer 0x%08X
Upper Threshold/Pause Packets 0x%08X
Lower Threshold/Pause Packets 0x%08X
Upper Threshold/High Priority 0x%08X
Lower Threshold/High Priority 0x%08X
Packet Counter 0x%08X
Level 0x%08X
Status 0x%04X
Control 0x%04X
Transmit 0x%04X
Receive 0x%04X
Transmit flow control 0x%04X
Transmit parameter 0x%04X
Serial mode 0x%04X
CSR Receive Queue 1 0x%08X
CSR Sync Queue 1 0x%08X
CSR Async Queue 1 0x%08X
CSR Receive Queue 2 0x%08X
CSR Async Queue 2 0x%08X
CSR Sync Queue 2 0x%08X
Write Pointer 0x%02X
Read Pointer 0x%02X
Level 0x%02X
Watermark 0x%02X
ISR Watermark 0x%02X
GMAC control 0x%04X
GPHY control 0x%04X
LINK control 0x%02hX
Control/Test 0x%08X
B
B B -B =B RB gB }B B B B B B cmd %08x = %08x
ethtool_regs
%-20s = %04x
%-20s = %04x
LAN911x Registers
index 1, MAC_CR = 0x%08X
index 2, ADDRH = 0x%08X
index 3, ADDRL = 0x%08X
index 4, HASHH = 0x%08X
index 5, HASHL = 0x%08X
index 6, MII_ACC = 0x%08X
index 7, MII_DATA = 0x%08X
index 8, FLOW = 0x%08X
index 9, VLAN1 = 0x%08X
index A, VLAN2 = 0x%08X
index B, WUFF = 0x%08X
index C, WUCSR = 0x%08X
PHY Registers
index 7, Reserved = 0x%04X
index 8, Reserved = 0x%04X
index 9, Reserved = 0x%04X
index 10, Reserved = 0x%04X
index 11, Reserved = 0x%04X
index 12, Reserved = 0x%04X
index 13, Reserved = 0x%04X
index 14, Reserved = 0x%04X
index 15, Reserved = 0x%04X
index 19, Reserved = 0x%04X
index 20, TSTCNTL = 0x%04X
index 21, TSTREAD1 = 0x%04X
index 22, TSTREAD2 = 0x%04X
index 23, TSTWRITE = 0x%04X
index 24, Reserved = 0x%04X
index 25, Reserved = 0x%04X
index 26, Reserved = 0x%04X
offset 0x50, ID_REV = 0x%08X
offset 0x54, INT_CFG = 0x%08X
offset 0x58, INT_STS = 0x%08X
offset 0x5C, INT_EN = 0x%08X
offset 0x60, RESERVED = 0x%08X
offset 0x64, BYTE_TEST = 0x%08X
offset 0x68, FIFO_INT = 0x%08X
offset 0x6C, RX_CFG = 0x%08X
offset 0x70, TX_CFG = 0x%08X
offset 0x74, HW_CFG = 0x%08X
offset 0x78, RX_DP_CTRL = 0x%08X
offset 0x7C, RX_FIFO_INF = 0x%08X
offset 0x80, TX_FIFO_INF = 0x%08X
offset 0x84, PMT_CTRL = 0x%08X
offset 0x88, GPIO_CFG = 0x%08X
offset 0x8C, GPT_CFG = 0x%08X
offset 0x90, GPT_CNT = 0x%08X
offset 0x94, FPGA_REV = 0x%08X
offset 0x98, ENDIAN = 0x%08X
offset 0x9C, FREE_RUN = 0x%08X
offset 0xA0, RX_DROP = 0x%08X
offset 0xA4, MAC_CSR_CMD = 0x%08X
offset 0xA8, MAC_CSR_DATA = 0x%08X
offset 0xAC, AFC_CFG = 0x%08X
offset 0xB0, E2P_CMD = 0x%08X
offset 0xB4, E2P_DATA = 0x%08X
index 0, Basic Control Reg = 0x%04X
index 1, Basic Status Reg = 0x%04X
index 2, PHY identifier 1 = 0x%04X
index 3, PHY identifier 2 = 0x%04X
index 4, Auto Negotiation Advertisement Reg = 0x%04X
index 5, Auto Negotiation Link Partner Ability Reg = 0x%04X
index 6, Auto Negotiation Expansion Register = 0x%04X
index 16, Silicon Revision Reg = 0x%04X
index 17, Mode Control/Status Reg = 0x%04X
index 18, Special Modes = 0x%04X
index 27, Control/Status Indication = 0x%04X
index 28, Special internal testability = 0x%04X
index 29, Interrupt Source Register = 0x%04X
index 30, Interrupt Mask Register = 0x%04X
index 31, PHY Special Control/Status Register = 0x%04X
Hardware Version %s
503_ISL3861 503_ISL3863 503 503_ACC 505 505_2958 505A 505AMX B B B B B B B B %x %s: %s =
%s:
%4zu Row %-*s %4zu %*s INT_ADR_KER INT_ADR_CHAR HW_INIT USR_EV_CFG EE_SPI_HCMD EE_SPI_HADR EE_SPI_HDATA EE_BASE_PAGE EE_VPD_CFG0 NIC_STAT GPIO_CTL GLB_CTL DP_CTRL MEM_STAT CS_DEBUG ALTERA_BUILD CSR_SPARE PCIE_SD_CTL0123 PCIE_SD_CTL45 PCIE_PCS_CTL_STAT EVQ_CTL EVQ_CNT1 EVQ_CNT2 BUF_TBL_CFG SRM_RX_DC_CFG SRM_TX_DC_CFG SRM_CFG SRM_UPD_EVQ SRAM_PARITY RX_FILTER_CTL RX_DC_PF_WM RX_RSS_TKEY RX_SELF_RST RX_RSS_IPV6_REG1 RX_RSS_IPV6_REG2 RX_RSS_IPV6_REG3 TX_CHKSM_CFG TX_RESERVED TX_PACE TX_VLAN TX_IPFIL_PORTEN MD_TXD MD_RXD MD_CS MD_PHY_ADR MD_ID MAC_STAT_DMA MAC_CTRL GEN_MODE MAC_MC_HASH_REG0 MAC_MC_HASH_REG1 GM_CFG1 GM_CFG2 GM_MAX_FLEN GM_ADR1 GM_ADR2 GMF_CFG0 GMF_CFG1 GMF_CFG2 GMF_CFG3 GMF_CFG4 GMF_CFG5 TX_SRC_MAC_CTL XM_ADR_LO XM_ADR_HI XM_GLB_CFG XM_TX_CFG XM_RX_CFG XM_MGT_INT_MASK XM_FC XM_PAUSE_TIME XM_TX_PARAM XM_RX_PARAM XX_PWR_RST XX_SD_CTL XX_TXDRV_CTL TX_IPFIL_TBL TX_SRC_MAC_TBL RX_DESC_PTR_TBL_KER RX_DESC_PTR_TBL TX_DESC_PTR_TBL_KER TX_DESC_PTR_TBL EVQ_PTR_TBL_KER EVQ_PTR_TBL BUF_FULL_TBL_KER BUF_FULL_TBL RX_MAC_FILTER_TBL0 TIMER_TBL TX_PACE_TBL RX_INDIRECTION_TBL TX_MAC_FILTER_TBL0 MC_TREG_SMEM RX_FILTER_TBL0 ADR_REGION0 ADR_REGION1 ADR_REGION2 ADR_REGION3 DRV_INT_EN_KER KER_INT_KER KER_INT_CHAR KER_INT_LEVE_SEL DRV_INT_EN_CHAR CHAR_INT_KER CHAR_INT_CHAR CHAR_INT_LEVE_SEL NORM_INT_VEC_DIS_KER NORM_INT_VEC_DIS_CHAR TLP_TD TD_SEL ATTR_SEL TLP_EP US_DISABLE WD_TIMER INTA_VEC INTB_VEC TLP_ATTR TLP_TC POST_WR_MASK FC_BLOCKING_EN B2B_REQ_EN PE_EIDLE_DIS TX_RREQ_MASK_EN DOORBELL_DROP TRGT_MASK_ALL TX_MRG_TAGS PCIE_CPL_TIMEOUT_CTRL BDMRD_CPLF_FULL DFLT_EVQ USREV_DIS EE_SPI_HCMD_ENC EE_SPI_HCMD_ADBCNT EE_SPI_HCMD_DUBCNT EE_SPI_HCMD_READ EE_SPI_HCMD_DABCNT EE_SPI_HCMD_SF_SEL EE_WR_TIMER_ACTIVE EE_SPI_HCMD_CMD_EN EE_SPI_HADR_ADR EE_SPI_HADR_DUBYTE EE_SPI_HDATA0 EE_SPI_HDATA1 EE_SPI_HDATA2 EE_SPI_HDATA3 EE_EXP_ROM_WINDOW_BASE EE_EXPROM_MASK EE_VPD_EN EE_VPD_EN_AD9_MODE EE_VPD_DEV_SF_SEL EE_VPD_ACCESS_BLOCK EE_VPD_ACCESS_ON EE_VPD_AD_SIZE EE_VPD_LENGTH EE_VPD_BASE EE_VPD_WR_CMD_EN EE_VPDW_BASE EE_VPDW_LENGTH EE_EE_WR_TMR_VALUE EE_EE_CLOCK_DIV EE_VPD_WIP_POLL EE_SF_CLOCK_DIV EE_SF_FASTRD_EN STRAP_PINS ATE_MODE EE_PRST SF_PRST ONCHIP_SRAM REVISION_ID EE_STRAP EE_STRAP_EN AER_DIS GPIO0_PWRUP_VALUE GPIO1_PWRUP_VALUE GPIO2_PWRUP_VALUE GPIO3_PWRUP_VALUE GPIO4_PWRUP_VALUE GPIO5_PWRUP_VALUE GPIO6_PWRUP_VALUE GPIO7_PWRUP_VALUE GPIO0_IN GPIO1_IN GPIO2_IN GPIO3_IN GPIO4_IN GPIO5_IN GPIO6_IN GPIO7_IN GPIO0_OUT GPIO1_OUT GPIO2_OUT GPIO3_OUT GPIO4_OUT GPIO5_OUT GPIO6_OUT GPIO7_OUT GPIO0_OEN GPIO1_OEN GPIO2_OEN GPIO3_OEN GPIO4_OEN GPIO5_OEN USE_NIC_CLK CLK156_OUT_EN GPIO8_PWRUP_VALUE GPIO9_PWRUP_VALUE GPIO10_PWRUP_VALUE GPIO11_PWRUP_VALUE GPIO12_PWRUP_VALUE GPIO13_PWRUP_VALUE GPIO14_PWRUP_VALUE GPIO15_PWRUP_VALUE GPIO8_IN GPIO9_IN GPIO10_IN GPIO11_IN GPIO12_IN GPIO13_IN GPIO14_IN GPIO15_IN GPIO8_OUT GPIO9_OUT GPIO10_OUT GPIO11_OUT GPIO12_OUT GPIO13_OUT GPIO14_OUT GPIO15_OUT GPIO8_OEN GPIO9_OEN GPIO10_OEN GPIO11_OEN GPIO12_OEN GPIO13_OEN GPIO14_OEN GPIO15_OEN GPIO_PWRUP_VALUE2 GPIO_IN2 GPIO_OUT2 GPIO_PWRUP_VALUE3 GPIO_IN3 GPIO_OUT3 SWRST EXT_PHY_RST_DUR INT_RST_DUR RST_CS RST_SF RST_TX RST_RX RST_SR RST_EV RST_EM RST_XGTX RST_XGRX RST_PCIE_CORE RST_PCIE_NSTKY RST_PCIE_STKY RST_BIU RST_PCIX RST_PCIE_SD RST_XAUI_SD RST_EXT_PHY HOT_RST_CTL CS_RST_CTL EE_RST_CTL SR_RST_CTL EV_RST_CTL EM_RST_CTL XGTX_RST_CTL XGRX_RST_CTL PCIE_CORE_RST_CTL PCIE_NSTKY_RST_CTL PCIE_STKY_RST_CTL BIU_RST_CTL PCIX_RST_CTL PCIE_SD_RST_CTL XAUI_SD_RST_CTL EXT_PHY_RST_CTL FLS_EVQ_ID MEM_PERR_VEC MBIST_ERR MBIST_CORR CS_DEBUG_EN CS_PORT_NUM ALTERA_BUILD_VER CSR_SPARE_BITS MEM_PERR_EN_TX_DATA MEM_PERR_EN PCIE_LODRV PCIE_HIDRV PCIE_RXEQCTL_L PCIE_RXEQCTL_H PCIE_TXTERMADJ_L PCIE_TXTERMADJ_H PCIE_RXTERMADJ_L PCIE_RXTERMADJ_H PCIE_PARLPBK PCIE_LPBK PCIE_LPBKWDRV_L PCIE_LPBKWDRV_H PCIE_PARRESET_L PCIE_PARRESET_H PCIE_HIVMODE_L PCIE_HIVMODE_H PCIE_OFFSETEN_L PCIE_OFFSETEN_H PCIE_OFFSET PCIE_TESTSIG_L PCIE_TESTSIG_H PCIE_DEQ0 PCIE_DEQ1 PCIE_DEQ2 PCIE_DEQ3 PCIE_DEQ4 PCIE_DEQ5 PCIE_DEQ6 PCIE_DEQ7 PCIE_DTX0 PCIE_DTX1 PCIE_DTX2 PCIE_DTX3 PCIE_DTX4 PCIE_DTX5 PCIE_DTX6 PCIE_DTX7 PCIE_PRBSSEL PCIE_PRBSERRACK_L PCIE_PRBSERRACK_H PCIE_PRBSSYNC_L PCIE_PRBSSYNC_H PCIE_CTCDISABLE_L PCIE_CTCDISABLE_H PCIE_FASTINIT_L PCIE_FASTINIT_H PCIE_PRBSERRH0 PCIE_PRBSERR PCIE_PRBSERRCOUNT0_L PCIE_PRBSERRCOUNT0_H EVQ_FIFO_NOTAF_TH EVQ_FIFO_AF_TH EVQ_OWNERR_CTL RX_EVQ_WAKEUP_MASK EVQ_ERR_REQ_CNT EVQ_CSR_REQ_CNT EVQ_EM_REQ_CNT EVQ_RX_REQ_CNT EVQ_TX_REQ_CNT EVQ_CNT_TOBIU EVQ_CNT_PRE_FIFO EVQ_TM_REQ_CNT EVQ_INIT_REQ_CNT EVQ_WET_REQ_CNT EVQ_WU_REQ_CNT EVQ_RDY_CNT EVQ_CLR_REQ_CNT EVQ_UPD_REQ_CNT BUF_TBL_MODE SRM_RX_DC_BASE_ADR SRM_CLK_TMP_EN SRM_TX_DC_BASE_ADR SRM_BANK_SIZE SRM_NUM_BANK SRM_INIT_EN SRM_OOB_BUF_INTEN SRM_OOB_ADR_INTEN SRM_UPD_EVQ_ID FORCE_SRAM_SINGLE_ERR FORCE_SRAM_PERR FORCE_SRAM_DOUBLE_ERR SEC_INT BYPASS_ECC RX_XOFF_MAC_EN RX_XOFF_MAC_TH RX_XON_MAC_TH RX_USR_BUF_SIZE RX_XOFF_TX_TH RX_XON_TX_TH RX_OWNERR_CTL RX_PCI_BURST_SIZE RX_RDW_PATCH_EN RX_DESC_PUSH_EN RX_HASH_INSRT_HDR RX_HASH_ALG RX_IP_HASH RX_INGR_EN RX_TCP_SUP RX_PRE_RFF_IPG RX_HDR_SPLIT_HDR_BUF_SIZE RX_HDR_SPLIT_PLD_BUF_SIZE RX_HDR_SPLIT_EN RX_MIN_KBUF_SIZE TCP_FULL_SRCH_LIMIT TCP_WILD_SRCH_LIMIT UDP_WILD_SRCH_LIMIT NUM_KER UDP_FULL_SRCH_LIMIT SCATTER_ENBL_NO_MATCH_Q UNICAST_NOMATCH_IP_OVERRIDE UNICAST_NOMATCH_RSS_ENABLED UNICAST_NOMATCH_Q_ID MULTICAST_NOMATCH_IP_OVERRIDE MULTICAST_NOMATCH_RSS_ENABLED MULTICAST_NOMATCH_Q_ID RX_VLAN_MATCH_ETHERTYPE RX_FILTER_ALL_VLAN_ETHERTYPES ETHERNET_FULL_SEARCH_LIMIT RX_DC_SIZE RX_MAX_PF RX_DC_PF_LWM RX_DC_PF_HWM RX_RSS_TKEY_LO RX_RSS_TKEY_HI RX_MAX_LU_LAT RX_MAX_PF_LAT RX_SELF_RST_EN RX_NODESC_WAIT_DIS RX_SW_RST_REG RX_ISCSI_DIS RX_RSS_IPV6_TKEY_LO RX_RSS_IPV6_TKEY_MID RX_RSS_IPV6_TKEY_HI RX_RSS_IPV6_TCP_SUPPRESS RX_RSS_IPV6_IP_THASH_ENABLE RX_RSS_IPV6_THASH_ENABLE TX_DC_SIZE TX_Q_CHKSM_DIS_0_31 TX_Q_CHKSM_DIS_32_63 TX_Q_CHKSM_DIS_64_95 TX_Q_CHKSM_DIS_96_127 TX_IP_ID_REP_EN TX_NON_IP_DROP_DIS TX_OWNERR_CTL TX_P1_PRI_EN TX_NO_EOP_DISC_EN TX_IP_ID_P0_OFS TX_FILTER_EN_BIT TX_VLAN_MATCH_ETHERTYPE_RANGE TX_FILTER_TEST_MODE_BIT TX_CONT_LOOKUP_THRESH_RANGE TX_MAX_PREF TX_MAX_CPL TX_IP_DIS TX_FLUSH_MIN_LEN_EN TX_TCP_DIS TX_DMA_SPACER TX_DMA_FF_THR TX_DIS_NON_IP_EV TX_ONE_PKT_PER_Q TX_PREF_THRESHOLD TX_ONLY1TAG TX_PREF_WD_TMR TX_PREF_SPACER TX_XP_TIMER TX_RX_SPACER_EN TX_PS_EVT_DIS TX_SOFT_EVT_EN TX_DROP_ABORT_EN TX_RX_SPACER TX_DMAQ_ST TX_DMAR_ST_P0 TX_D_FF_FULL_P0 TX_PUSH_CHK_DIS TX_PUSH_EN TX_RD_COMP_TMR TX_PREF_AGE_CNT TX_EVT_CNT TX_PACE_BIN_TH TX_PACE_FB_BASE TX_PACE_SB_AF TX_PACE_SB_NOT_AF TX_VLAN0 TX_VLAN0_PORT0_EN TX_VLAN0_PORT1_EN TX_VLAN1 TX_VLAN1_PORT0_EN TX_VLAN1_PORT1_EN TX_VLAN2 TX_VLAN2_PORT0_EN TX_VLAN2_PORT1_EN TX_VLAN3 TX_VLAN3_PORT0_EN TX_VLAN3_PORT1_EN TX_VLAN4 TX_VLAN4_PORT0_EN TX_VLAN4_PORT1_EN TX_VLAN5 TX_VLAN5_PORT0_EN TX_VLAN5_PORT1_EN TX_VLAN6 TX_VLAN6_PORT0_EN TX_VLAN6_PORT1_EN TX_VLAN7 TX_VLAN7_PORT0_EN TX_VLAN7_PORT1_EN TX_VLAN_EN TX_IPFIL0_PORT_EN TX_IPFIL1_PORT_EN TX_IPFIL2_PORT_EN TX_IPFIL3_PORT_EN TX_IPFIL4_PORT_EN TX_IPFIL5_PORT_EN TX_IPFIL6_PORT_EN TX_IPFIL7_PORT_EN TX_IPFIL8_PORT_EN TX_IPFIL9_PORT_EN TX_IPFIL10_PORT_EN TX_IPFIL11_PORT_EN TX_IPFIL12_PORT_EN TX_IPFIL13_PORT_EN TX_IPFIL14_PORT_EN TX_IPFIL15_PORT_EN TX_IPFIL16_PORT_EN TX_IPFIL17_PORT_EN TX_IPFIL18_PORT_EN TX_IPFIL19_PORT_EN TX_IPFIL20_PORT_EN TX_IPFIL21_PORT_EN TX_IPFIL22_PORT_EN TX_IPFIL23_PORT_EN TX_IPFIL24_PORT_EN TX_IPFIL25_PORT_EN TX_IPFIL26_PORT_EN TX_IPFIL27_PORT_EN TX_IPFIL28_PORT_EN TX_IPFIL29_PORT_EN TX_IPFIL30_PORT_EN TX_IPFIL31_PORT_EN TX_MADR0_FIL_EN MD_WRC MD_RDC MD_RIC MD_PRSP MD_GC MD_INT_CLR MD_PL MD_PT MD_ADDR_CMD MD_WR_EN_CMD MD_RD_EN_CMD MD_DEV_ADR MD_PRT_ADR MAC_STAT_DMA_ADR MAC_STAT_DMA_CMD MAC_SPEED MAC_LINK_STATUS MAC_UC_PROM MAC_BCAD_ACPT MAC_XG_DISTXCRC TXFIFO_DRAIN_EN MAC_XOFF_VAL XG_PHY_INT_MASK XFP_PHY_INT_MASK XG_PHY_INT_POL_SEL XFP_PHY_INT_POL_SEL MAC_MCAST_HASH0 MAC_MCAST_HASH1 GM_TX_EN GM_SYNC_TXEN GM_RX_EN GM_SYNC_RXEN GM_TX_FC_EN GM_RX_FC_EN GM_LOOP GM_RST_TX_FUNC GM_RST_RX_FUNC GM_RST_TX_MAC_CTL GM_RST_RX_MAC_CTL GM_SIM_RST GM_SW_RST GM_FD GM_CRC_EN GM_PAD_CRC_EN GM_LEN_CHK GM_HUGE_FRM_EN GM_IF_MODE GM_PAMBL_LEN GM_ADR_B3 GM_ADR_B2 GM_ADR_B1 GM_ADR_B0 GM_ADR_B5 GM_ADR_B4 GMF_HSTRSTWT GMF_HSTRSTSR GMF_HSTRSTFR GMF_HSTRSTST GMF_HSTRSTFT GMF_WTMENREQ GMF_SRFENREQ GMF_FRFENREQ GMF_STFENREQ GMF_FTFENREQ GMF_WTMENRPLY GMF_SRFENRPLY GMF_FRFENRPLY GMF_STFENRPLY GMF_FTFENRPLY GMF_CFGXOFFRTX GMF_CFGFRTH GMF_CFGLWM GMF_CFGHWM GMF_CFGFTTH GMF_CFGHWMFT GMF_HSTFLTRFRM GMF_HSTFLTRFRMDC GMF_HSTDRPLT64 GMF_CFGBYTMODE GMF_HSTSRFULLCLR GMF_SRFULL GMF_CFGHDPLX TX_MAC_QID_SEL TX_DROP_CTR_CLR TX_SRC_FLTR_EN TX_SRC_DROP_CTR XM_CORE_RST XM_INTCLR_MODE XM_WAN_MODE XM_RX_JUMBO_MODE XM_TX_STAT_EN XM_RX_STAT_EN XM_DEBUG_MODE XM_RMTFLT_GEN XM_TX_RST XM_TXEN XM_TX_PRMBL XM_AUTO_PAD XM_EDRC XM_TXCRC XM_FCNTL XM_IPG XM_TX_PROG XM_RX_RST XM_RXEN XM_RX_PRMBL XM_RXCRC XM_AUTO_DEPAD XM_ACPT_ALL_UCAST XM_ACPT_ALL_MCAST XM_REJ_BCAST XM_PASS_PRMBLE_ERR XM_PASS_CRC_ERR XM_PASS_LENERR XM_MSK_LCLFLT XM_MSK_RMTFLT XM_MSK_PRMBLE_ERR XM_MSK_STAT_CNTR_OF XM_MSK_STAT_CNTR_HF XM_MSK_STA_INTR XM_DIS_FCNTL XM_XMIT_PAUSE XM_ZPAUSE XM_REJ_CNTL_MCAST XM_REJ_CNTL_UCAST XM_MCNTL_PASS XM_TX_MAC_STAT XM_RX_MAC_STAT XM_RX_PAUSE_CNT XM_TX_PAUSE_CNT XM_PAD_CHAR XM_MAX_TX_FRM_SIZE_LO XM_MAX_TX_FRM_SIZE_HI XM_TX_JUMBO_MODE XM_MAX_RX_FRM_SIZE_LO XM_MAX_RX_FRM_SIZE_HI XX_RST_XX_EN XX_RSTXGXSTX_EN XX_RSTXGXSRX_EN XX_RESETA_EN XX_RESETB_EN XX_RESETC_EN XX_RESETD_EN XX_RSTPLLAB_EN XX_RSTPLLCD_EN XX_PWRDNA_EN XX_PWRDNB_EN XX_PWRDNC_EN XX_PWRDND_EN XX_SD_RST_ACT XX_RSTXGXSTX_SIG XX_RSTXGXSRX_SIG XX_RESETA_SIG XX_RESETB_SIG XX_RESETC_SIG XX_RESETD_SIG XX_RSTPLLAB_SIG XX_RSTPLLCD_SIG XX_SIM_MODE XX_PWRDNA_SIG XX_PWRDNB_SIG XX_PWRDNC_SIG XX_PWRDND_SIG XX_LPBKA XX_LPBKB XX_LPBKC XX_LPBKD XX_LODRVA XX_HIDRVA XX_LODRVB XX_HIDRVB XX_LODRVC XX_HIDRVC XX_LODRVD XX_HIDRVD XX_TERMADJ0 XX_TERMADJ1 XX_DTXA XX_DTXB XX_DTXC XX_DTXD XX_DEQA XX_DEQB XX_DEQC XX_DEQD TX_IP_SRC_ADR_0 TX_IPFIL_MASK_0 TX_IP_SRC_ADR_1 TX_IPFIL_MASK_1 TX_SRC_MAC_ADR_0 TX_SRC_MAC_ADR_1 JUMBO LABEL OWNER BUF_BASE SW_WPTR DC_HW_RPTR PREF_ACT HDIG DDIG RX_RESET HDR_SPLIT FLUSH !TCP_CHKSM !IP_CHKSM !NON_IP_DROP IP_FILT ETH_FILT Q_MASK_WIDTH EVQ_BUF_BASE_ID EVQ_SIZE EVQ_EN EVQ_NXT_WPTR EVQ_DOS_PROTECT_EN EVQ_WKUP_OR_INT_EN EVQ_RPTR_IGN BUF_OWNER_ID_FBUF BUF_ADR_FBUF BUF_ADR_REGION IP_DAT_BUF_SIZE BUF_FULL_UNUSED RMFT_VLAN_ID RMFT_DEST_MAC RMFT_WILDCARD_MATCH RMFT_RXQ_ID RMFT_IP_OVERRIDE RMFT_SCATTER_EN RMFT_RSS_EN TIMER_MODE RELOAD_TIMER_VAL HOST_NOTIFY_MODE INT_PEND INT_ARMD TIMER_Q_EN IT_QUEUE TMFT_VLAN_ID TMFT_SRC_MAC TMFT_WILDCARD_MATCH TMFT_TXQ_ID MC_TREG_SMEM_ROW SRC_PORT SRC_IP DEST_PORT DEST_IP TCP_UDP C "C B `"C RB "C B "C B #C B #C B $C B $C B %C B @%C B %C B %C B &C B @'C B +C B .C B .C $B `.C -B .C :B .C DB .C TB @0C bB @1C tB 2C |B 2C B 3C B p3C B 3C B 3C B 3C B 4C B 4C wB 4C B `6C B `7C B 7C B 7C B 7C B 8C B 08C *B @8C B 8C ;B 8C mB 8C HB :C TB ;C \B B ̀ NB \ \B jB vB B B B B B B B B B B /B BB RB eB sB B @ B ` B B B B B B B B &B 4B @B 8 QB ^B Ї mB ` B B B B B B B B B B B B B B +B =B OB aB sB B B B B B B B B B B B B B B B #B -B 7B AB KB UB _B iB sB }B B B B B B B B B B -B 6B ?B IB SB ]B gB qB {B B B B B B B B B B B B B B B B 'B @ 9B H BB P LB ` ^B h gB p qB wB B B B B B B B B B B B B B B B B B *B 6B ( BB MB {B B XB cB nB yB B B B B B B B B B B B +B 5B B 5 @B LB ( XB iB xB H B B @ B B B B B B B B B B ( 'B 7B GB WB gB vB B B B 8 B B B B B B B B B B B )B $ 3B ( =B , GB 0 QB 4 [B 8 eB < oB |B B B B B B B B B B ( B 0 5B 4 JB \B kB zB zB B B B ( B < B P B d B B C C ( ) C < 8 C P D C T T C h d C q C C C C C C C C C C C &C <C DC OC ^C ^C mC mC {C C {C C C C C C C C C C C C C C C C C %C 1 4C NC hC ǀ xC H C C C C C C C C 1C + FC dC C 9 C E C Հ C V QC ^ C C C C C (C @ 7C EC SC bC uC C C C C C C C C &C :C OC @ dC ` zC C C C C C C C 0 RC (RC A PRC I xRC Q RC Y RC a RC i C !C r =C IC TC ^C rC }C C C C C C C C , C C C !C 0C AC @ NC YC р gC Հ wC C ـ C C w C C C C C C C C (C 1C CC UC ^C pC C 0 C C C @ C C C P C C C ` C $ C 6 C p ? C Q C c C n C C C C C C C C C
C "
C 5
C H
C [
C n
C
C
C
C
C
C
C
C C C , C ? C R C e C x C C C C C tB {B C C C C C C C C C C ' C B 4 C ? C J C [ C l C v C C C C C C C C C
C
C %
C 5
C >
C K
C T
C a
C m
C y
C
C
C
C
C
C
C
C
C
C
C C C C B (C 2C <C FC PC ZC dC qC ~C C C C C C C C C C C C C ,C ;C GC RC ]C iC vC C C C C C C C C C C KB UB C 'C 6C BC SC aC oC }C C C C C C C C C C C C C C C C (C :C GC ZC jC yC C C C C C C C C C C (C 6C EC B TC dC tC C C C C C C C C C #C 0C =C JC YC hC uC C C C C C C C C C C C $C 0C >C LC ZC hC qC zC C C C C C C C C C C C C C C C C C $C ,C 4C DC TC @ dC ` tC C @ C C C C C C
B C $ C 8 C D C P C ր C ׀ C C ـ C ڀ C C C C C
B C $ C 8 C D C P C ր C ׀ C C C C C ܀ C ݀ #C ^ 0C @C IC PC ]C pC C C C C 0 C C C C C
C = C ɀ *C ʀ :C ˀ XC XC FC FC QC bC sC |C C TB C C C C C = C C C C 0 C @ C ` C /C ?C ETHERNET_WILDCARD_SEARCH_LIMIT TX_FILTER_ALL_VLAN_ETHERTYPES_BIT TX_TCPIP_FILTER_FULL_SEARCH_RANGE TX_TCPIP_FILTER_WILD_SEARCH_RANGE TX_UDPIP_FILTER_FULL_SEARCH_RANGE TX_UDPIP_FILTER_WILD_SEARCH_RANGE TX_ETH_FILTER_FULL_SEARCH_RANGE TX_ETH_FILTER_WILD_SEARCH_RANGE ST GMAC Registers
Reg%d 0x%08X
DMA Registers
ST MAC 10/100 Registers
control reg 0x%08X
addr HI 0x%08X
addr LO 0x%08X
multicast hash HI 0x%08X
multicast hash LO 0x%08X
MII addr 0x%08X
MII data %08X
flow control 0x%08X
VLAN1 tag 0x%08X
VLAN2 tag 0x%08X
mac wakeup frame 0x%08X
mac wakeup crtl 0x%08X
CSR%d 0x%08X
DMA cur tx buf addr 0x%08X
DMA cur rx buf addr 0x%08X
rmgr: Location out of range
Added rule with ID %d
Filter: %d
Rule Type: TCP over IPv4
Rule Type: UDP over IPv4
Rule Type: SCTP over IPv4
SPI: %d mask: 0x%x
Rule Type: Raw IPv4
Unknown Flow type: %d
Action: Drop
IPv6 flows not implemented
rxclass: Unknown flow type
Total %d rules
ip4 Invalid %s value[%s]
%s-mask Invalid %s mask[%s]
Add rule, invalid syntax
src-ip dst-ip tos src-port dst-port action loc vlan-etype user-def spi l4proto l4data src dst rmgr: Cannot delete RX class rule rxclass: Cannot get RX class rule count rmgr: Cannot allocate memory for RX class rule locations rmgr: Cannot get RX class rules rmgr: Invalid RX class rules table size rmgr: Cannot allocate memory for RX class rules rmgr: Cannot find appropriate slot to insert rule
rmgr: Cannot insert RX class rule Src IP addr: %s mask: %s
Dest IP addr: %s mask: %s
TOS: 0x%x mask: 0x%x
Src port: %d mask: 0x%x
Dest port: %d mask: 0x%x
Rule Type: IPSEC AH over IPv4
Rule Type: IPSEC ESP over IPv4
Protocol: %d mask: 0x%x
L4 bytes: 0x%x mask: 0x%x
Flow Type: Raw Ethernet
Src MAC addr: %02X:%02X:%02X:%02X:%02X:%02X mask: %02X:%02X:%02X:%02X:%02X:%02X
Dest MAC addr: %02X:%02X:%02X:%02X:%02X:%02X mask: %02X:%02X:%02X:%02X:%02X:%02X
Ethertype: 0x%X mask: 0x%X
VLAN EtherType: 0x%x mask: 0x%x
VLAN: 0x%x mask: 0x%x
User-defined: 0x%llx mask: 0x%llx
Action: Direct to queue %llu
rxclass: Cannot get RX class rule rxclass: Cannot allocate memory for RX class rule locations rxclass: Cannot get RX class rules Add rule, unrecognized option[%s]
sA vA vA vA sA sA sA sA sA LvA LvA sA sA uA sA sA sA sA tA |A A kA A ՀA A 9A A jA A F~A A ;A A ʃA A TA A ڂA bA )A <|A
VC L VC P VC @ X VC T %VC V .VC 5VC 9VC @ A B DVC D
VC L VC P VC @ X MVC 0 T .VC 5VC 9VC @ A B DVC D
VC L VC P VC @ X QVC Z YVC 0 T MVC 0 T VC T %VC V .VC 5VC 9VC @ A B DVC D `VC
R dVC
L SVC X .VC 5VC 9VC @ A B DVC D %-20s: Identifier : 0x%02x (GBIC)
(SFP)
(reserved or unknown)
Extended identifier : 0x%02x (unknown)
Connector : 0x%02x (unknown or unspecified)
(SC)
(BNC/TNC)
(FibreJack)
(MT-RJ)
(MU)
(SG)
(Optical pigtail)
(MPO Parallel Optic)
(HSSDC II)
(Copper pigtail)
(RJ45)
%s 10G Ethernet: 10G Base-LR
%s 10G Ethernet: 10G Base-SR
%s Infiniband: 1X SX
%s Infiniband: 1X LX
%s SONET: OC-48, long reach
%s SONET: OC-48, short reach
%s SONET: OC-12, short reach
%s SONET: OC-3, short reach
%s Ethernet: BASE-PX
%s Ethernet: BASE-BX10
%s Ethernet: 100BASE-FX
%s Ethernet: 100BASE-LX/LX10
%s Ethernet: 1000BASE-T
%s Ethernet: 1000BASE-CX
%s Ethernet: 1000BASE-LX
%s Ethernet: 1000BASE-SX
%s FC: short distance (S)
%s FC: long distance (L)
%s FC: medium distance (M)
%s FC: Longwave laser (LC)
%s FC: Longwave laser (LL)
%s FC: Copper Active
%s FC: Copper Passive
%s FC: Copper FC-BaseT
%s FC: Twin Axial Pair (TW)
%s FC: Twisted Pair (TP)
%s FC: Miniature Coax (MI)
%s FC: Video Coax (TV)
%s FC: Multimode, 50um (M5)
%s FC: Single Mode (SM)
%s FC: 1200 MBytes/sec
%s FC: 800 MBytes/sec
%s FC: 400 MBytes/sec
%s FC: 200 MBytes/sec
%s FC: 100 MBytes/sec
Encoding : 0x%02x (unspecified)
(8B/10B)
(4B/5B)
(NRZ)
(Manchester)
(SONET Scrambled)
(64B/66B)
%-20s: %u%s
MBd BR, Nominal Rate identifier : 0x%02x km Length (SMF,km) Length (SMF) Length (50um) Length (62.5um) Length (Copper) Length (OM3) Passive Cu cmplnce. : 0x%02x (unspecified) (SFF-8431 appendix E) (unknown) [SFF-8472 rev10.4 only]
Active Cu cmplnce. : 0x%02x (SFF-8431 limiting) Laser wavelength : %unm
Vendor name Vendor PN Vendor rev : => (no module present, unknown, or unspecified)
(module soldered to motherboard)
(GBIC not specified / not MOD_DEF compliant)
(GBIC/SFP defined by 2-wire interface ID)
(GBIC compliant with MOD_DEF %u)
(Fibre Channel Style 1 copper)
(Fibre Channel Style 2 copper)
(Fibre Channel coaxial headers)
Transceiver codes : 0x%02x 0x%02x 0x%02x0x%02x 0x%02x 0x%02x 0x%02x 0x%02x
%s 10G Ethernet: 10G Base-ER [SFF-8472 rev10.4 only]
%s 10G Ethernet: 10G Base-LRM
%s Infiniband: 1X Copper Active
%s Infiniband: 1X Copper Passive
%s ESCON: ESCON MMF, 1310nm LED
%s ESCON: ESCON SMF, 1310nm Laser
%s SONET: OC-192, short reach
%s SONET: SONET reach specifier bit 1
%s SONET: SONET reach specifier bit 2
%s SONET: OC-48, intermediate reach
%s SONET: OC-12, single mode, long reach
%s SONET: OC-12, single mode, inter. reach
%s SONET: OC-3, single mode, long reach
%s SONET: OC-3, single mode, inter. reach
%s FC: very long distance (V)
%s FC: intermediate distance (I)
%s FC: Shortwave laser, linear Rx (SA)
%s FC: Electrical inter-enclosure (EL)
%s FC: Electrical intra-enclosure (EL)
%s FC: Shortwave laser w/o OFC (SN)
%s FC: Shortwave laser with OFC (SL)
%s FC: Multimode, 62.5um (M6)
(4/2/1G Rate_Select & AS0/AS1)
(8/4/2G Rx Rate_Select only)
(8/4/2G Independent Rx & Tx Rate_Select)
(8/4/2G Tx Rate_Select only)
Vendor OUI : %02x:%02x:%02x
A A yA cA MA 7A !A A A ߋA ɋA A A ;A ;A ;A ;A ;A ;A ;A ;A ;A ;A ;A ;A ;A ;A ;A ;A ;A ;A ;A A qA [A
A A A ˌA #A A A A wA aA KA ύA fC ; s p x p 8 pP P 0 ` x б H кX P P pp P
P
00 @ ` 0 @ @ @
0
` `P p ` H P "8 @#X `6 < E P`` d h k l Џp X P 8 h @ p @ ` @ 0h p H @` H p ` 0 8 ` 0 @
P `p ( ( zR x # D^ 4 4 { BED A(D0d(A ABBd l ] BEE B(A0A8FP
8A0A(B BBBD w
8F0A(B BBBJ , AMK
CAG < BGJ D(I0q(A OBB 4 D 0 BNA A(D0(C ABB | أ P L BDD D(F0
(A ABBI W(K ABB $ AGK
AA L $ BBB H(A0C8J`
8A0A(B BBBF t Ш& D , f AIDPP
AAA (+ @ 4 H AG@
AD S
AD ~
AI , $ LMQ
D L T BNB B(A0A8DT
8A0A(B BBBH | 0{ BBB B(A0A8GP
8A0A(B BBBB N
8F0A(B BBBC B
8F0A(B BBBA , $ 0 AGPX
AG x
AA $ T MN@{
J 4 | BAA
AED SAE $ p: MQ
A < BBA D(Gk
(A ABBG 4 ( BAA GP
AABE $ T MS0r
F , | ( MX@6
E ȼL D0c
I V
A $ K AG
AG L BBE E(A0A8D`
8A0A(B BBBD 4 D ` AAG X
AAE N
FAC , | ؿ AGPX
AG x
AA , AJ
AE X
AA L AAG`^
CAE d
FAE N
FAK T
CAA , D D 0 BBB A(A0G<
0A(A BBBE L BBB B(A0A8D:
8A0A(B BBBF n MI0W $ k ML
F 4 $ P5 BAA J
AABH , \ Xb AG y
AF S
AA d g BBB B(D0F8GPp
8A0A(B BBBE
8F0A(B BBBA $ MN@`
A , l AG0k
AD V
AA L L Hb BBB B(A0A8J
8A0A(B BBBE L h{ BBB B(D0D8Gp
8A0A(B BBBA D BKA G_
AABH A
FABA < 4
AKG
AAG
FAI D t
ASD@
FAB S
AAK J
FAA T
# BHD G~
FABD ]
AABG Q FAB , ` AIG
AAF 4 D BFD G"
AABG , | M`
C d BBB B(A0A8Dp
8A0A(B BBBE |
8C0A(B BBBA D BHD G<
AABK A
FABF D \ X: BHD G
AABG A
FABF D P BHD G
AABI A
FABF L ( BBB B(A0C8G
8A0A(B BBBD T <
E BOH G(D0MP
0C(A BBBG b0C(A BBB
i A@
O FL
BBB B(A0A8G
8C0A(B BBBJ $ $- gr
G $ , * M[z
F d T 3 BGB B(A0A8DJ
8A0A(B BBBI =
8C0A(B BBBG , M AKM CA < xQ BLA C(K
(C ABBJ 4 , UC AIDPJ
AAF CA d X L | hY5# BGE B(A0A8D`"
8A0A(B BBBA , X| BDE
ABD |2 L }
" BIB B(A0D8P
8C0A(B BBBJ L d BHI B(A0E8O@
8C0A(B BBBF $ @ ]Np L ( BGB B(D0A8K]
8A0A(B BBBD , , x BDA
ABH 4 \ BIA I(D@(C ABB, BHI x
ABR 4 0o BRD s
ARL AAB , h& AHL <
FAP , , h ANL d
KAM \ H A{ | H A D 8 ACG )
FAM e
AAQ DIA 4 8 AML
FAG eAA 4 M ADG
FAR D
IAR $ T [ AKP lKA | A $ N ASF qAA , BHD
ADF A , a BKA
ADB , D j BSE JAD , t P AHS bCA ? Dz 4 BGA D(D0(A ABBL P BGB B(A0A8D`C
8A0A(B BBBH , D BXD AD , t & BOA AD $ MN@P
E $ H MNPe
H O Dj
B q GJ
G , 4 P ADJi
AAF , d M^
G $ P. MZ
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